Field of the Invention
The present invention relates to a thin film transistor (TFT) substrate. More particularly, the present invention relates to a TFT substrate applied to a flexible display apparatus.
Discussion of the Related Art
Thin film transistors (TFTs) are being widely used as switching devices of display apparatuses such as liquid crystal display (LCD) apparatuses, organic light emitting display apparatuses, etc. Therefore, a TFT substrate where a plurality of TFTs are formed is a fundamental element of a display apparatus.
Research on flexible display apparatuses is being actively done. Since it is required for the flexible display apparatuses to be bent or wound, instead of glass, a polymer material such as polyimide (PI) or the like is used as a material of a substrate configuring a base of a TFT substrate.
Hereinafter, a related art TFT substrate which uses a polymer material, such as PI or the like, as a material of a substrate will be described.
FIG. 1 is a schematic cross-sectional view of a related art TFT substrate.
As seen in FIG. 1, the related art TFT substrate includes a substrate 10, a first buffer layer 15, a blocking layer 20, a second buffer layer 25, an active layer 30, a first gate insulation layer 35, a first gate electrode 40, a second gate insulation layer 45, a second gate electrode 50, an interlayer dielectric 55, a source electrode 60a, a drain electrode 60b, a passivation layer 65, a planarization layer 70, and a pixel electrode 80.
The substrate 10, as described above, is formed of a polymer material such as PI or the like.
The first buffer layer 15 is formed on the substrate 10.
The blocking layer 20 is formed on the first buffer layer 15. The blocking layer 20 is formed between the substrate 10 and the active layer 30 and prevents a movement of an electron in a channel area of the active layer 30, from being adversely affected by a component included in the substrate 10.
The second buffer layer 25 is formed on the blocking layer 20.
The active layer 30 is formed on the second buffer layer 25. The active layer 30 includes a channel area 31, a plurality of low-concentration doping areas 32 which are respectively provided at a left side and a right side of the channel area 31, and a plurality of high-concentration doping areas 33 which are respectively provided at a left side of one of the low-concentration doping areas 32 and a right side of the other of the low-concentration doping areas 32.
The first gate insulation layer 35 is formed between the active layer 30 and the first gate electrode 40, and the first gate electrode 40 is formed on the first gate insulation layer 35.
The second gate insulation layer 45 is formed between the first gate electrode 40 and the second gate electrode 50, and the second gate electrode 50 is formed on the second gate insulation layer 45.
The interlayer dielectric 55 is formed on the second gate electrode 50, and the source electrode 60a and the drain electrode 60b are formed on the interlayer dielectric 55. The source electrode 60a is connected to one of the high-concentration doping areas 32 of the active layer 30 through a first contact hole CH1, and the drain electrode 60b is connected to the other of the high-concentration doping areas 32 through a second contact hole CH2.
The passivation layer 65 is formed on the source electrode 60a and the drain electrode 60b, and the planarization layer 70 is formed on the passivation layer 65.
The pixel electrode 80 is formed on the planarization layer 70. The pixel electrode 80 is connected to the drain electrode 60b through a third contact hole CH3.
FIGS. 2A to 2I are diagrams illustrating a process of manufacturing the related art TFT substrate.
First, as seen in FIG. 2A, the first buffer layer 15 is formed on the substrate 10, the blocking layer 20 is pattern-formed on the first buffer layer 15, and the second buffer layer 25 is formed on the blocking layer 20.
A first mask process is performed for forming a pattern of the blocking layer 20. In the present specification, a mask process denotes a pattern forming process that includes an exposure process using a mask for obtaining a structure of a certain pattern. Although not shown, the blocking layer 20 is connected to an external signal driver at an outer portion of the substrate 10. To this end, the blocking layer 20 extends to the outer portion of the substrate 10, and a process of forming a contact hole in the second buffer layer 25 is performed for exposing a portion of the blocking layer 20 at the outer portion of the substrate 10. A second mask process is performed for forming the contact hole.
Subsequently, as seen in FIG. 2B, a semiconductor layer 30a for an active layer is pattern-formed on the second buffer layer 25, and the first gate insulation layer 35 is formed on the semiconductor layer 30a for the active layer. A third mask process is performed for pattern-forming the semiconductor layer 30a for the active layer.
Subsequently, as seen in FIG. 2C, the first gate electrode 40 is pattern-formed on the first gate insulation layer 35. A fourth mask process is performed for pattern-forming the first gate electrode 40.
After the first gate electrode 40 is pattern-formed, a low-concentration dopant is doped on the semiconductor layer 30a for the active layer by using the first gate electrode 40 as a mask. Therefore, an area where the low-concentration dopant is not doped becomes the channel area 31, and the low-concentration doping areas 32 are respectively formed at the left side and right side of the channel area 31. Subsequently, although not shown, a photoresist pattern is formed on the first gate insulation layer 35, and then, by using the photoresist pattern as a mask, the high-concentration doping areas 33 are respectively formed at the left side of one of the low-concentration doping areas 32 and the right side of the other of the low-concentration doping areas 32. As a result, the active layer 30 which includes the channel area 31, the low-concentration doping areas 32 which are respectively provided at a left side and a right side of the channel area 31, and the high-concentration doping areas 33 which are respectively provided at a left side of one of the low-concentration doping areas 32 and a right side of the other of the low-concentration doping areas 32 are finished. In this case, a fifth mask process is performed for forming the photoresist pattern for forming each of the high-concentration doping areas 33.
Subsequently, as seen in FIG. 2D, the second gate insulation layer 45 is formed on the first gate electrode 40, and the second gate electrode 50 is pattern-formed on the second gate insulation layer 45. A sixth mask process is performed for pattern-forming the second gate electrode 50.
Subsequently, as seen in FIG. 2E, the interlayer dielectric 55 is formed on the second gate electrode 50, and the first contact hole CH1 and the second contact hole CH2 are formed for exposing the high-concentration doping areas 33 of the active layer 30. A seventh mask process is performed for forming the first contact hole CH1 and the second contact hole CH2. In addition, a thermal treatment process for activation is performed before the first contact hole CH1 and the second contact hole CH2 are formed.
Subsequently, as seen in FIG. 2F, the source electrode 60a and the drain electrode 60b which are respectively connected to the high-concentration doping areas 32 of the active layer 30 through the first and second contact holes CH1 and CH2 are pattern-formed. An eighth mask process is performed for forming the source electrode 60a and the drain electrode 60b. 
Subsequently, as seen in FIG. 2G, the passivation layer 65 is formed on the source electrode 60a and the drain electrode 60b, and the third contact hole CH3 is formed for exposing the drain electrode 60b. A ninth mask process is performed for forming the third contact hole CH3. A thermal treatment process for hydrogenation is performed before the third contact hole CH3 is formed. By performing the thermal treatment process for hydrogenation, hydrogen (H) included in the passivation layer 65 is diffused to the active layer 30, and thus, the dangling bonds of the active layer 30 are reduced.
Subsequently, as seen in FIG. 2H, the planarization layer 70 is formed on the passivation layer 65, and then, the third contact hole CH3 is formed for exposing the drain electrode 60b. The third contact hole CH3 is obtained by removing a portion of the planarization layer 70 over the passivation layer 65 and within the opening in the passivation layer 65 formed in the previous process using the ninth mask, to thereby expose again the surface of the drain electrode 60b. Illustratively, the third contact hole CH3 is formed in two separate processes, first forming an opening in the passivation layer 65 (before the planarization layer 70 is formed) and second, in a subsequent process, after having formed the planarization layer 70, removing material of the planarization layer 70 over and in the opening in the passivation layer 65. A tenth mask process is performed for obtaining the third contact hole CH3 by removing a portion of the planarization layer 70.
Subsequently, as seen in FIG. 2I, the pixel electrode 80 which is connected to the drain electrode 60b through the third contact hole CH3 is pattern-formed. An eleventh mask process is performed for pattern-forming the pixel electrode 80.
As described above, in the related art TFT substrate, since a total eleven-time mask process is needed, a process is very complicated.